Optimizations for the implementation of a turbo decoder

Turbo decoding techniques achieve near-optimal performance in terms of Bit Error Rate (BER) at low Signal to Noise Ratios (SNR's). Amongst these techniques, convolutional turbo codes and product turbo codes are nowadays the most common ones. They have already been selected as a standard for the Universal Mobile Telecommunication System (UMTS) [Lit. 4]. In the future, they will probably also be selected as a standard for Wireless Local Area Networks (WLAN). For such high-speed wireless applications, throughput and energy consumption are crucial issues. By contrast, the hardware implementation of the turbo codes is rather slow and power consuming. Therefore, the implementation of turbo decoders needs to be optimized. Since an analysis of the energy consumption and throughput in turbo decoders has indicated a bottleneck in memory accesses, a systematic data transfer and storage optimization methodology, developed at IMEC, has been applied. It reduces the energy consumption and latency; in addition, it allows reaching higher data rates. The whole methodology has been applied to the convolutional turbo decoder, while for the product turbo decoder only some global optimizations have been exploited. Based on a high-level memoryand architectural model, estimations have been made for area, energy per bit, throughput and latency at a constant clock frequency of 77 MHz. For the convolutional turbo code, a 25-fold energy reduction per decoded bit has been achieved, while at the same time the speed is multiplied by 400 and the latency divided by 400. These results have been achieved at the cost of the logicand memory area: the total area consumption is increased by a factor of 5. The results of the product turbo code show a gain in both energyand area consumption: the energy consumption per decoded bit is decreased with a factor 5 and the area consumption is decreased with a factor 3. For the throughput and latency of the product turbo code, no estimations have been made in this report. The energy consumption per decoded bit of the convolutional turbo code after optimization (0.04 I-lJ) has acceptable levels for an implementation at high datarates. The product turbo code, however, still needs some optimizations before it can be implemented on a single chip, as the energy consumption per bit (0.6 I-lJ) is still too large for a high-speed implementation.